Traditionally, SRAM (Static Random Access Memory) is designed by tiling together instances of a bitcell into a bitcell array. An individual bitcell may be optimized to achieve various objectives. For example, for some applications a bitcell may be optimized for high density at the expense of relatively slow read and write operations, whereas for other applications a bitcell may be optimized for high speed operation at the expense of occupying a larger die area.